A sub-logarithmic time sorting algorithm on a reconfigurable array

A sub-logarithmic time sorting algorithm on a reconfigurable array

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Article ID: iaor19921827
Country: Japan
Volume: E74
Issue: 11
Start Page Number: 3894
End Page Number: 3901
Publication Date: Nov 1991
Journal: Transactions of the Institute of Electronics, Information and Communication Engineers
Authors: , ,
Keywords: combinatorial analysis
Abstract:

A bus system whose configuration can be dynamically changed is called a reconfigurable bus system. A reconfigurable array consists of processors arranged to a 2-dimensional grid with a reconfigurable bus system. The authors present a parallel algorithm which sorts N elements in equ1 time on a reconfigurable array with equ2processors for every equ3. [In Japanese.]

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