Probabilistic modeling and fault analysis in sequential logic using computer simulation

The problem of detecting permanent faults in sequential circuits by random testing is analyzed utilizing a continuous parameter Markov model. Given a sequential circuit with certain stuck faults specified, the original state table and its error version can be readily derived from an analysis of the circuit under fault-free and faulty conditions, respectively. By simulation of these two tables on a computer, the parameters of the desired Markov model can be obtained. The present approach does not require formulation of a product state table corresponding to the fault-free state table and its faulty version, which is rather difficult while dealing with large circuits. For a specified confidence degree, it is easy to derive the parameters of the model and to calculate either the required lengths of random test patterns or the maximum testing time. A complete mathematical analysis of the model is given that provides some useful insights into the nature of faults in relation to random testing and the associated confidence degree.