Article ID: | iaor20097401 |
Country: | United Kingdom |
Volume: | 2 |
Issue: | 2 |
Start Page Number: | 81 |
End Page Number: | 89 |
Publication Date: | Jul 2008 |
Journal: | Journal of Simulation |
Authors: | Chwif L, Muniz P S, Shimada L M |
Keywords: | verification |
Verification and Validation (V&V) is a key process to guarantee that any model represents adequately a given system. Although no one can guarantee a 100% valid model, it is possible to increase model confidence by the utilization of V&V techniques. There are many V&V techniques that have a descriptive nature (they tell us what to do but not how to do it). There are also prescriptive techniques, that tell us how to do it, but in simulation practice they are very underused. The objective of this paper is to propose a prescriptive V&V technique that is simple enough for practical application and, because of its procedural nature, it could be easily built into any simulation software, thus enabling the automation of the V&V process. This approach was also applied to some test problems in the literature and also to a real–life consultancy project confirming its feasibility.