Dynamic capacity modeling in semiconductor assembly manufacturing

It is very challenging to gain a competitive advantage in semiconductor assembly manufacturing, mainly due to widely and quickly fluctuating customer requests, complicated workflows, and the co-existence of new and aging technology/equipment. In late 2003, Intel Shanghai experienced capacity degradation, mainly due to the introduction of multiple-chip products with re-entrant workflows. In response, we applied the joint protective capacity methodology to semiconductor assembly manufacturing and developed a dynamic capacity model that captures the variability of re-entrant manufacturing systems.