Evaluating order of circuits for deadlock avoidance in a flexible manufacturing system

In modern highly automated flexible manufacturing systems, various parts are processed concurrently. Due to the concurrency and shared equipment usage, deadlock is a common problem that causes loss of productivity. When such a system is modelled by a digraph, existence of circuits in such a graph is a necessary condition for deadlock and knots and the order of circuits are closely related to impending deadlocks – a type of deadlock that is more difficult to detect. A deadlock avoidance algorithm that dynamically evaluates the order of circuits is presented. The algorithm is highly permissive since the order evaluation captures more part flow dynamics, especially when there exist multiple knots in the digraph model. It also runs in polynomial time once the set of circuits of the digraph is given. Simulation results are provided to illustrate the application of the algorithm.