Article ID: | iaor20052125 |
Country: | United Kingdom |
Volume: | 32 |
Issue: | 2 |
Start Page Number: | 327 |
End Page Number: | 341 |
Publication Date: | Feb 2005 |
Journal: | Computers and Operations Research |
Authors: | Fowler John W., Carlyle W. Matthew, Perez Imelda C. |
Keywords: | heuristics |
The diffusion step in semiconductor wafer fabrication is very time consuming, compared to other steps in the process, and performance in this area has a significant impact on overall factory performance. Diffusion furnaces are able to process multiple lots of similar wafers at a time, and are therefore appropriately modeled as batch processing machines with incompatible job families. Due to the importance of on-time delivery in semiconductor manufacturing, we focus on minimizing the total weighted tardiness in this environment. The resulting problem is NP-Hard, and we decompose it into two sequential decision problems: assigning lots to batches followed by sequencing the batches. We develop several heuristics for these subproblems and test their performance.