Capacity-constrained scheduling for a logic integrated circuit final test facility

A capacity-constrained scheduling using the concept of the theory of constraints for a semiconductor Logic IC final test operation is presented. The scheduling of the IC final test considers unrelated parallel machines with multiple constraint problems. A broad product mix, variable lot sizes and yields, long and variable set-up times, as well as limited test equipment capacity characterize the operations in this test facility. Discrete event simulation models based on e-M-plant™ are developed to implement the capacity-constrained scheduling algorithm. A comparison is also made with other rules, which are combinations of the rules such as first come first serve and earliest due date for the order scheduling, and the rules such as minimum set-up time, shortest processing time and shortest set-up time plus processing time for the dispatching test equipment. The simulation results show that the proposed capacity-constrained scheduling outperforms other rules for the committed volume performance in many different operational conditions. Directions for future research are also presented.