Modelling and analysis of wafer fabrication scheduling via generalized stochastic Petri net and simulated annealing

Some of the important characteristics of the semiconductor wafer fabrication factories are re-entrant process flows, a dynamic and uncertain environment, stringent production control requirements, etc. that pose a major challenge to the scheduling decisions in integrated circuit wafer fabrication process. Keeping in view the high capital investment and quick response to the market changes, it is essential for the integrated circuit fabrication process to exercise effective control on its production operations so that production resources can be employed in a flexible and efficient manner. The present research has focused on the development of a generalized stochastic Petri net model that faithfully captures dynamic behaviours such as re-entrant processing, machine failures, loading and unloading, etc., pertaining to wafer fabrication. A simulated annealing-based scheduling strategy using mean cycle time and tardiness as performance measures was also developed to obtain an efficient and robust schedule for a known hard problem. Analysis of variance was applied to examine the interaction effects of various scheduling rules and to identify the main as well as the interaction effects of dispatching rules, dispatching rules and set-up rules, and set-up rules and batching rules. Paired t-tests were applied to assess the performance of rule combinations for lot and batch scheduling. The proposed simulated annealing-based solution methodology was tested on a well-known data set adopted from the literature and its performance reveals that simulated annealing-based scheduling rules work better than existing rules in terms of the two performance measures mean cycle time and tardiness.