Branch history register cache

Modern superscalar processors highly depend on efficient branch prediction to exploit a large amount of instruction level parallelism. However, it is known that branch prediction accuracy is degraded when process switches are present. At the same time, multithreading architectures are considered a good approach to increase the total throughput. In multithreading architectures, however, the process switch rate is very high and even a second level cache miss causes a process switch. In such an environment, branch prediction is severely degraded. In this paper, we propose a hardware technique to reduce the impact of process switches. This technique consists of adding a cache to store the branch history register on a process switch. We show that this scheme reduces the impact of process switches significantly especially when process switches occur very frequently.