Systematic layout planning; A study on semiconductor wafer fabrication facilities

Systematic layout planning; A study on semiconductor wafer fabrication facilities

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Article ID: iaor20012643
Country: United Kingdom
Volume: 20
Issue: 12
Start Page Number: 1360
End Page Number: 1372
Publication Date: Jan 2000
Journal: International Journal of Operations & Production Management
Authors: , ,
Keywords: layout, electronics industry
Abstract:

This paper proposes to use Muther's systematic layout planning procedure as the infrastructure to solve a fabrication layout design problem. A multiple objective decision-making tool, analytic hierarchy process, is then proposed to evaluate the design alternatives. The proposed procedure is illustrated to be a viable approach for solving a fabrication layout design problem through a real-world case study. It features both the simplicity of the design process and the objectivity of the multiple-criteria evaluation process as opposed to existing solution methodologies.

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