Reduced simulation models of wafer fabrication facilities

Detailed simulation models of large wafer fabrication facilities can require substantial amounts of computer execution time. Practitioners and researchers have frequently embraced the notion that, if detail must be sacrificed, it is wise to reduce detail for the low-utilization workstations. However, a specific prescription for how to reduce the detail and empirical evidence of the validity of the approximation has been lacking. In this paper we show that acccurate estimates of total cycle time and equipment utilization may be obtained using reduced fabrication simulation models that replace operations at low-utilization workstations with fixed time lags. We demonstrate the accuracy of the approximation on industrial data. The criterion we use for deleting workstations from the model is the standard deviation of lot waiting time. The computer execution time for such reduced models is five to ten times less than that for complete models of the fabrication.