Scan-chain optimization methods for very large system integration

Scan-chain optimization methods for very large system integration

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Article ID: iaor20002191
Country: Japan
Volume: 40
Issue: 4
Start Page Number: 1651
End Page Number: 1659
Publication Date: Apr 1999
Journal: Transactions of Information Processing Society of Japan
Authors: ,
Keywords: design, graphs
Abstract:

This paper presents a scan-chain optimization method for multiple scan-paths. The proposed method first determines pairs of scan-in and scan-out pins using pin locations. Then, flip-flops are assigned to the pairs by a graph theoretical method, and three Travelling Salesman Problem methods optimize connection-order of flip-flops. Experimental results show the effectiveness of the proposed method.

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