The authors discuss the upper and lower bounds on an area to embed an n-vertex and d-degree graph (d≥5; called (n,d)-graph) on an extended VLSI model. On this model, a vertex with degree more than 4 is embedded in some region rather than a grid point and wires may pass through any vertex region. On the other hand, some usual VLSI model forbids it. This paper examines whether embedded area for (n,d)-graph can be reduced or not when the VLSI model is extended as such. They show that for any n and d there exists an (n,d)-graph whose area requires ¦[(n2d2) if both width and height of any vertex region are at least ¦[(d). If the restriction of vertex region is relaxed, any (n,d)-graph can be embedded with O(n2d) area and this upper bound is the best possible under the relaxed restriction. [In Japanese.]
