‘Topological via minimization’ problem for permutation layout when no wire passes between pins

‘Topological via minimization’ problem for permutation layout when no wire passes between pins

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Article ID: iaor199738
Country: Japan
Volume: 77
Issue: 9
Start Page Number: 32
End Page Number: 41
Publication Date: Sep 1994
Journal: Electronics and Communications in Japan, Part III Fundamental Electronic Science
Authors: , ,
Keywords: layout
Abstract:

This paper considers the topological via minimization problem in the permutation layout, under the constraint that no wire passes between pins which are adjacent on the same horizontal line. Under a constraint that the upper side of the upper horizontal line not be used as the wiring area, an algorithm is proposed with time complexity equ1 for equ2 and equ3 for the general value of k, for the problem of determining the set of maximum k-layer wiring (n is the number of nets). Then an algorithm is proposed with time complexity equ4 for the case where the wiring can be the whole plane.

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