Article ID: | iaor199738 |
Country: | Japan |
Volume: | 77 |
Issue: | 9 |
Start Page Number: | 32 |
End Page Number: | 41 |
Publication Date: | Sep 1994 |
Journal: | Electronics and Communications in Japan, Part III Fundamental Electronic Science |
Authors: | Abe M., Araki T., Kashiwabara T. |
Keywords: | layout |
This paper considers the topological via minimization problem in the permutation layout, under the constraint that no wire passes between pins which are adjacent on the same horizontal line. Under a constraint that the upper side of the upper horizontal line not be used as the wiring area, an algorithm is proposed with time complexity