Balanced block spacing for VLSI layout

Placement algorithms for VLSI layout tend to stick the building blocks togehter. The results in the need to increase the space between adjacent blocks to allow the routing of interconnecting wires. The above problem is called the block spacing problem. This paper presents a model for spreading the blocks uniformly over the chip area, to accommodate the routing requirements, such that the desired adjacency relations between the blocks are retained. The block spacing problem is solved via a graph model, whose vertices represent the building blocks, and its arcs represent the space between adjacent blocks. Then, the desired uniform spacing can be presented as a space balancing problem. In this paper the existence and unqiueness of a solution to the one dimensional space balancing problem are proved, and an iterative algorithm which converges rapidly to the solution is presented. It is shown that in general, the two dimensional problem may have no solution.