Yield analysis of partial defect tolerant bit‐plane array

Silicon complexity places long‐stand paradigms at risk. Key concerns include increasing process variations, defect rates, infant mortality rates, and susceptibility to internal and external noises. These trends are likely to decrease functional yield. Fabrication of die with 100% working transistors and interconnections becomes prohibitively expensive. This paper examines the size and the position of the candidate part of the architecture for defect tolerance application, for the given topology and defect probability where yield can be improved in comparison to error tolerant design. In order to achieve the mentioned goal, we modified the existing mathematical description of yield by involving error tolerant concept introducing a function $G\left(a\right)$ that models the topology of architecture. The evaluation is demonstrated on the bit‐plane semi‐systolic array, as a relatively complex array topology. The method that we hereby present for the chosen topology is described and proved in formal mathematical way, and it easily covers simpler topologies. It will be shown that partial involvement of defect tolerant design can significantly improve effective yield for defect rates which are common in nanotechnology.