Performance‐Driven Layer Assignment by Integer Linear Programming and Path‐Constrained Hypergraph Partitioning

Performance‐driven physical layout design is becoming increasingly important for both high speed integrated circuits and printed circuit boards. This paper studies the problem of assigning wire segments into two layers so as to minimize the number of vias, while taking into account performance constraints such as layer preference and circuit timing. We show that using the Elmore delay model, three timing problems in synchronous digital circuits–the long path problem, the short path problem and the time skew problem–can be formulated as a set of linear inequalities. We use the model of signed hypergraph to represent two‐layer routings and formulate the performance‐driven optimum layer assignment problem as the path‐constrained maximum balance problem in a signed hypergraph. Two solution methods are developed and implemented. First, an integer linear programming formulation is derived for finding exact solutions. Second, a local‐search heuristic for hypergraph partitioning is extended to cope with path‐inequality constraints. Experimental results on a set of layer‐assignment benchmarks demonstrated that the path‐constrained local‐search heuristic achieves optimum or near‐optimum solutions with several orders of magnitude faster than the integer linear programming approach.