A nonlinear optimization methodology for VLSI fixed-outline floorplanning

Floorplanning is a critical step in the physical design of VLSI circuits. The floorplanning optimization problem can be formulated as a global optimization problem minimizing wire length, with the area of each rectangular module fixed while the module's height and width are allowed to vary subject to aspect ratio constraints. While classical floorplanning seeks to simultaneously minimize the wire length and the area of the floorplan without being constrained by a fixed outline for the floorplan, state–of–the–art technologies such as System–On–Chip require the solution of fixed–outline floorplanning. Fixing the outline of the floorplan makes the problem significantly more difficult. In this paper, we propose a two–stage nonlinear–optimization–based methodology specifically designed to perform fixed–outline floorplanning by minimizing wire length while simultaneously enforcing aspect ratio constraints on soft modules and handling a zero deadspace situation. In the first stage, a convex optimization globally minimizes an approximate measure of wire length. Using the solution of the first stage as a starting point, the second stage minimizes the wire length by sizing the modules subject to the prescribed aspect ratios, and ensuring no overlap. Computational results on standard benchmarks demonstrate that the model is competitive with other floorplanning approaches in the literature.