Article ID: | iaor20091240 |
Country: | South Korea |
Volume: | 34 |
Issue: | 3 |
Start Page Number: | 296 |
End Page Number: | 307 |
Publication Date: | Sep 2008 |
Journal: | Journal of the Korean Institute of Industrial Engineers |
Authors: | Faaland Bruce, Suh Jungdae |
Keywords: | scheduling |
A semiconductor production system has sophisticated manufacturing operations and needs high capital investment for its expensive equipment, which warrants efficient real-time flow control for wafers. In the bay, we consider material handling equipment that can handle multiple carriers of wafers. The dispatching logic first determines the transportation time of each carrier to its destination by each unit of transportation equipment and uses this information to determine the destination machine and target carrier. When there is no available buffer space at the machine tool, the logic allows carriers to stay at the buffer of a machine tool and determine the delay time, which is used to determine the destination of carriers in URL. A simulation study shows this dispatching logic performs better than the procedure currently in use to reduce the mean flow time and average WIP of wafers and increase efficiency of material handling equipment.