Emulating concurrency in a circuit card assembly system

Typical component-placement systems for populating surface mount technology printed circuit boards now exhibit a high degree of concurrency in their functional operations. This concurrency ideally yields high ‘burst-rate’ estimates of throughput. However, if the concurrency is not properly understood and exploited, the burst rate is severely degraded, as exhibited by process rates observed in the actual production environment. This discernment requires an experimental characterization of the systems’ functional operation, which must also reflect the peculiarities of the controller. Such an experimental analysis is an essential precursor to performance-optimization procedures of numerically controlled flexible manufacturing systems. This article describes the present analysis of an extremely complex workcell with a high degree of concurrency. Due to its enveloping complexity, the methodological framework for the analysis should be applicable to a broad class of concurrent systems. Empirically verifying the characterization required the development of an emulator that quantitatively defines the system to be modeled. As such, it is a numerical, off-line design and analysis tool. It has been utilized to obtain the process rate for particular products, preevaluate proposed engineering changes, interactively construct setups and sequences, and obtain parameters required for line-balancing procedures.