Area minimization of regular array structure of custom very large system integration

The problem under consideration is area minimization of two-dimensional array-based structures of custom VLSI. Approaches to solving two tied problems are presented. The first problem is logic minimization of functional representation of the control logic realized by array-based structure that is done during logic design stage. The second one is topological compaction aimed at minimization the chip area occupied by the array structure and it is solved at topological level before layout generation.