Trees, slices, and wheels: On the floorplan area minimization problem

Hierarchical approaches to floorplan design usually use trees to represent hierarchical floorplans, defining topological relations between a set of components to be placed on a (circuit) board. This placement is then optimized to minimize chip area, perimeter, or other such cost measurements. This work places the problem of minimizing heirarchical floorplans of order k within the appropriate theoretical framework and presents an algorithm that uses exclusively the k-ary representation tree to determine the best or minimal solution to a conflicting bicriteria problem. The algorithm does not need predefined partitioning schemes and determines the orientation of each individual component. It can deal both with five-module wheels, as well as slices, and can handle an arbitrary number of realizations for each individual component.