Simulated annealing and parallel processing: An implementation for constrained global design optimization

Global optimization becomes important as more and more complex designs are evaluated and optimized for superior performance. Often parametic designs are highly constrained, adding complexity to the design problem. In this work simulated annealing (SA), a stochastic global optimization technique, is implemented by augmenting it with a feasibility improvement scheme (FIS) that makes it possible to formulate and solve a constrained optimization problem without resorting to artificially modifying the objective function. The FIS is also found to help recover from the infeasible design space rapidly. The effectiveness of the improved algorithm is demonstrated by solving a welded beam design problem and a two part stamping optimization problem. Large scale practical design problems may prohibit the efficient use of computationally intensive iterative algorithms such as SA. Hence the FIS augmented SA algorithm is implemented on an Intel iPSC/860 parallel super-computer using a data parallel structure of the algorithm for the solution of large scale optimization problems. The numerical results demonstrate the effectiveness of the FIS as well as the parallel version of the SA algorithm. Expressions are developed for the estimation of the speedup of iterative algorithms running on a parallel computer with hyper-cube interconnection topology. Computational speedup in excess of 8 is achieved using 16 processors. The timing results given for the example problems provide guidelines to designers in the use of parallel computers for iterative processes.