Multistage interconnection networks in multiprocessor systems. A simulation study

The principal modelling and simulation features of multistage interconnection networks operating in packet switching are discused in this paper. The networks studied interconnect processors and memory modules in multiprocessor systems. Several methods are included to increase the bandwidth achievable with this kind of networks. Besides using network buffering, the possibility of having queues of requests at the memory modules is considered. Network conflicts can be reduced using a second network to return requests from the memory modules. The connection of more than one processor or memory module to each of the multistage network input or output lines allows the interconnection of large multiprocessor systems using small multistage networks. This is implemented using a single shared bus connection. The effective bandwidth of these networks is compared to that of circuit switching multistage networks and Crossbar. Simulation results reflect an important improvement in network performance.