Performance evaluation of buffer management schemes for implementing ATM cell reassembly mechanism

An automated teller machine (ATM) switching system may be designed so that communications between processors of its control part can be performed via its switching network rather than a separate inter-processor communications (IPC) network. In such a system, there should be interfaces to convert IPC traffic from message format to cell format and vice versa, that is, mechanisms to perform the SAR (Segmentation And Reassembly) sublayer functions. In this paper, we consider the cell reassembly mechanism among them, mainly focused on buffer management schemes. We consider a few alternatives to implement cell reassembly function block, namely, separated buffering, reserved buffering and shared buffering in this paper. In case of separated and reserved buffering, we employ a continuous time Markov chain for the performance evaluation of cell reassembly mechanism, judicially defining the states of the mechanism. Performance measures such as message loss probability, mean number of messages queued in buffer and average reassembly delay are obtained in closed forms. In case of shared buffering, we compare the alternatives for implementing cell reassembly function block using simulation because it is almost impossible to analyze the mechanism of shared buffering by analytical modeling. Some illustrations are given for the performance analysis of the alternatives to implement cell reassembly function block.