Gigaflops in linear programming

Gigaflops in linear programming

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Article ID: iaor19971094
Country: Netherlands
Volume: 18
Issue: 4
Start Page Number: 157
End Page Number: 165
Publication Date: Feb 1996
Journal: Operations Research Letters
Authors: ,
Keywords: computational analysis: supercomputers
Abstract:

This paper describes the parallelization of an ‘industrial strength’ linear programming package. The present parallel version of CPLEX Barrier, running on a Silicon Graphics Power Challenge shared-memory multiprocessor, provides dramatic performance improvements over sequential methods on a wide range of practical, realistic linear programming problems. The resulting software/hardware combination can provide sustained performance of as much as 2.4Gflops.

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