A preliminary model for lot sizing in semiconductor manufacturing

In this paper, the authors develop a preliminary mathematical model for determining lot sizes for a single product which has several quality levels. The quality level of each unit is determined (‘binned’) by testing the product after it is produced. Binning based on performance after production is common in several industries, but the application which motivated the model developed here is semiconductor manufacture. A typical example is a microprocessor that operates at one of several different speeds. Specifically, consider the 80486 microprocessor developed by Intel Corporation of Santa Clara, California. (The 486 chip is currently the processor of choice for IBM compatible personal computers.) At the current time, the 486 operates at three speeds: 25, 33 and 50MHz. The production process is exactly the same in each case. After the chip is produced, it is tested and binned based on its performance. The issue that is addressed in this paper is to determine the value of the lot size (x) so guaranteeing with specified probabilities that the demands for the various grades of product are satisfied. It is also assumed, as is often done for problems of this type, that higher quality products may be substituted for ones of lower quality, but not vice versa. While several related studies have addressed similar issues in more general settings, the present approach will yield a solution which is easy to compute and easy to implement.